vhd2vl
VHDL to Verilog translator
What is vhd2vl?
Where can I download it?
What is vhd2vl?
Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001. It does not support the full VHDL grammar - most of the testbench-related features have been left out.
While different synthesizers support slightly different templates and language subsets, the basic pattern of expressing logic within the language is pretty clear. As of the 2.2 release, vhd2vl supports:
- File organization using entity and architecture.
- Signal declaration: time, natural, positive, integer (synonyms), boolean, std_logic, std_ulogic (synonyms), signed, unsigned, std_logic_vector, std_ulogic_vector (synonyms), and enumerations ("type" keyword).
- Bit ranges (to, downto).
- Module instantiation (component declarations are parsed but ignored).
- Processes triggered on clock events or expressions.
- Control logic: if/elsif/else/end if, case, for.
- All arithmetic and boolean unary and binary operators.
- "After" clauses.
Vhd2vl is written using lex (actually Flex), yacc (actually Bison), and C. It should build and run in just about any POSIX-compatible environment.